1. Field of the Invention
The present invention relates to processors, and more specifically to processors that increase performance through the specialized handling of repetitive operations.
2. Description of the Related Art
In applications such as signal transmission applications, the quality of a transmission signal can deteriorate to the extent that the information received at the output of the channel is of doubtful quality. In a typical system, the transmitted information signal is temporally convoluted in a conventional manner, with the convoluted mode including forbidden states or conformations for the received signals. Therefore, in reception it is sufficient for the received information elements (generally a pair of bits) to compute a set of information elements to be sent. These information elements, when convoluted with respect to one another, are likely to have had the received information as the result. The information elements are convoluted with the previous, and previously received, information elements. It is possible, for these previous information elements, to perform the same analysis. Thus, it is possible to go back in time in correspondence with the information elements previously received. Further, any forbidden states arrived at by the operations for going back in time could not have actually been sent, so these states must be eliminated.
For simplicity, it can be assumed that for a pair of bits received it is necessary on 256 previous occurrences to compute the meaning of the pair of bits transmitted at the beginning of these 256 occurrences. In other words, at each pair of bits received, the 256 previous occurrences are taken into account. To achieve the bit rates typically desired (e.g., one megabit per second in speech processing), the signal processor must be capable of performing up to 256 processing operations in less than one microsecond. Further, the elementary operations that must be performed for the processing operations include multiplication accumulation ("MAC") operations. For example, for each of the 256 processing operations described above, the computation of 8 or 16 elementary MAC operations can be required.
In conventional processors, repetitive operations (i.e., the 8 or 16 elementary operations) are performed by having the processor load a counter register with the value 8 or 16 at the beginning of the series. Then, the processor launches one iteration of the MAC function, decrements the counter by one, and compares the counter value with a reference value. As long as the two values are not equal, the processor repeats this process (i.e., performs another iteration). When the macro-operation MAC is completed, the processor can proceed to the next processing operation of the 256 processing operations to be performed. Because for each elementary operation the processor must generate commands to load the counter register, decrement it, and compare it with a reference value, the processor must be very fast to allow processing to be completed within the required time.
To overcome this drawback, it has been proposed to install coprocessors or multicycle instructions. However, the designing of a coprocessor and the designing of a multicycle instruction have the drawback of requiring prior knowledge of the nature of the instruction to be performed. For example, for the processing operations described above, a coprocessor would be designed to perform the predetermined 16 MAC steps. Therefore, if it later becomes desirable to be able perform 24 such steps, the coprocessor must be changed. With respect to multicycle instructions, a sequencer or state machine similarly defines the executable operations (and it may even replace the processor for certain simple instructions). Because the sequencer is permanently fixed, the set of executable instructions cannot be extended by the addition of new repeatable instructions.